1. Field of the Invention
The present invention is related to processing systems and processors, and more specifically to a method of operating a pipelined processor core with reconfigurable architecture.
2. Description of Related Art
In present-day processor cores, pipelines are used to execute multiple hardware threads corresponding to multiple instruction streams, so that more efficient use of processor resources can be provided through resource sharing and by allowing execution to proceed even while one or more hardware threads are waiting on an event.
In existing systems, specific resources and pipelines are typically provided in a given processor design, the execution resource types are fixed and in many instances, particular types of execution resources may be absent from certain processor cores, while other processor core types may have different execution resources. In some instances, resources within a processor core will remain unused except when needed on rare occasions, consuming die area that might otherwise be used to increase processor core performance.
It would therefore be desirable to provide methods for processing program instructions that provide improved used of the processor core resources.